Technical Field
The present disclosure regards a vertical conduction integrated electronic device that is protected against the so-called “latch-up” phenomenon; further, the present disclosure regards the corresponding manufacturing process.
Description of the Related Art
As is known, electronic devices are today available, such as for example MOSFETs or insulated-gate bipolar transistors (IGBTs), which are able to conduct high currents and withstand high voltages. These devices, however, may be subjected to the so-called latch-up phenomenon.
For instance, as shown in FIG. 1 with reference to an IGBT 1, this transistor has a parasitic circuit, which includes a first parasitic transistor 2 and a second parasitic transistor 3, which are, respectively, of a PNP and an NPN type. In addition, the collector of the first parasitic transistor 2 is connected to the base of the second parasitic transistor 3, the collector of which is connected to the base of the first parasitic transistor 2, whereas the emitters of the first and second parasitic transistors 2, 3 are connected to the drain terminal and to the source terminal, respectively, of the IGBT 1. This being said, in latch-up conditions, the first and second parasitic transistors 2, 3 form a closed path flowing in which is a current that is self-sustaining, irrespective of the value of the voltage that controls the IGBT 1. Likewise, in the case of a power MOSFET (not shown), in latch-up conditions, within the corresponding body region, and thus between the source and drain, a current is found to flow also in the case where the gate terminal is set at a zero voltage, which entails, in practice, the impossibility of switching off the MOSFET.